This invention relates to memory cells which use fuses to permanently store data in integrated circuits.
FIG. 1 shows an exemplary memory cell 10 for storing one bit of data in an integrated circuit. The stored bit may be part of a chip identification number, may indicate to a decoder whether a redundant circuit should be used in place of a main circuit, may store a default value to be used by control circuitry of the integrated circuit, or may be used for a variety of other purposes.
Memory cell 10 includes a fuse 12 and a latch 14. Fuse 12 stores the bit of data. During power-up of the integrated circuit, the information stored by fuse 12 is read by the circuitry to which the information applies. To read the information during power-up, a recharging signal (bFPUP) first recharges latch 12. Next, a read signal (FPUN) cause the information stored in fuse 12 to be output as the BIT signal. If fuse 12 is not blown, the FPUN signal causes node N to be grounded and, hence, causes the BIT signal to be high. If fuse 12 is blown, node N remains high which causes the BIT signal to be low.
FIG. 2 shows an exemplary integrated circuit lay out for two adjacent memory cells of the type shown in FIG. 1. Each one of these memory cells can use, for example, a six transistor latch 14 to store and allow reading a single bit of data. In some implementations, each one of the latches 14 occupies close to 1.5 times the layout area required by a single fuse 12. In addition, each one of latches 14 can increase the pitch of memory cell 10 (that is, the minimum required space between adjacent memory cells) to be more than that required by fuse 12.
Referring to FIG. 3, in a highly integrated circuit, thousands of fuse and latch memory cells may be used. To read them during power-up, significant current is required. Such a high current can damage the integrated circuit. Hence, instead of reading all of the memory cells at the same time, the memory cells in the integrated circuit are organized into memory cell banks which are then read sequentially according to a predetermined sequence. In FIG. 3, for example, line 14 shows the sequence by which memory cell banks BK are read. To implement the sequence, buffers are used to delay the bFpup and FPUN signals from one memory cell bank to the next. These buffers require additional space on the integrated circuit chip.